Víctor Soria Pardos

Ph.D. Candidate in Computer Architecture @ Universitat Politècnica de Catalunya (UPC) and Barcelona Supercomputing Center (BSC-CNS)

About Me

I earned my diploma on Computer Science from Universidad de Zaragoza (Unizar). Soon after, I started working at Barcelona Supercomputing Center (BSC-CNS) while I pursued my Master in Innovation and Research in Informatics at Universitat Politècnica de Catalunya (UPC) Currently, I am a 1st year Ph.D. student in Computer Architecture. My supervisors are Dr. Adrià Armejach from UPC/BSC-CNS, Dr. Darío Suárez from Unizar and Dr. Miquel Moretó from UPC/BSC-CNS.

My research interests include several topics of computer architecture. Specifically, my research focuses in parallel computing, compiler support, and developing microarchitectural prediction mechanisms. As side project, I collaborate in the Drac Project.

Recent News

[2025] Our paper Delegato: Locality-Aware Atomic Memory Operations on Chiplets was accepted at MICRO 25.

[2025] Our paper FLAMA: Architecting Floating-Point Atomic Memory Operations for Heterogeneous HPC Systems was accepted at DSD 25.

[2024] Our paper GenArchBench: A genomics benchmark suite for arm HPC processors was accepted at FGCS.

[2023] I intershiped in Arm Sophia Antipolis for three months.

[2023] I participated in ACACES 2023 with a poster about coherence prediction

[2023] Our paper A Tensor Marshaling Unit for Sparse Tensor Algebra on General-Purpose Processors was accepted at MICRO 23.

[2023] Our paper DynAMO: Improving Parallelism Through Dynamic Placement of Atomic Memory Operations was accepted at ISCA 23.

[2022] Our paper Sargantana: A 1 GHz+ In-Order RISC-V Processor with SIMD Vector Extensions in 22nm FD-SOI got accepted at DSD 2022 and received the Outstanding Paper Award.

[2022] I obtained my Master in Master in Innovation and Research in Informatics

[2021] Arm has published a short blog entry about my research

[2021] Received the FPU Competitive Doctoral Fellowship by the Spanish Government after.

[2021] I participated in ACACES 2021 with a poster about far AMO

Education

Universitat Politècnica de Catalunya (UPC)

Ph.D. Candidate in Computer Architecture

November 2021 - now

Supervisors: Miquel Moretó, Adrià Armejach, Darío Suárez

Universitat Politècnica de Catalunya (UPC)

Master in Innovation and Research in Informatics. Specialization in High Performance Computing

September 2019 - January 2022

Universidad de Zaragoza (Unizar)

Bachelor's Degree in Informatics Engineering

September 2015 - July 2019

One year abroad at Universitat Politècnica de Catalunya

Thesis: Characterization of HPC applications for ARM SIMD instructions

Caracterización de aplicaciones HPC para extensiones vectoriales de ARM

Professional Experience

Teaching Assistant @ Universitat Politècnica de Catalunya (UPC)

September 2023 - December 2025

Computer Architecture (2023,2024,2025)
Computer Architecture II (2024,2025)

First Stage Researcher (PhD Student) @ Barcelona Supercomputing Center (BSC-CNS)

September 2021 - December 2025

Participation in Projects:
- EPI SGA2
- Arm Center of Excellence
- ACAP: Arquitectura de Computadores de Altas Prestaciones
- BZL: Barcelona Zettascale Lab
Thesis: Advanced Atomics: Leveraging Memory Hierarchies to Improve Atomic Memory Operations for Next Generation Coherent Manycores

Junior Research Engineer @ Barcelona Supercomputing Center (BSC-CNS)

September 2019 - September 2021

Participation in Projects:
- Drac
- Arm Center of Excellence
Characterizing AMO in Arm machines

Undergraduate Research Student @ Barcelona Supercomputing Center (BSC-CNS)

September 2018 - September 2019

Participation in Projects:
- Montblanc 2020
Characterizing SIMD extensions using OpenMP autovectorization

Publications

2025

[MICRO'25] Delegato: Locality-Aware Atomic Memory Operations on Chiplets

V. Soria-Pardos, A. Armejach, D. Suárez-Gracia, T. Mück, J. A. Joao, M. Moretó.. Proceedings of the 58th Annual International Symposium on Microarchitecture (MICRO 2025).

[DSD'25] FLAMA: Architecting Floating-Point Atomic Memory Operations for Heterogeneous HPC Systems

V. Soria-Pardos, A. Armejach, D. Suárez-Gracia, D. Martinot, A. Grasset, M. Moretó. Euromicro Conference on Digital System Design (DSD 2025), Salerno.

2024

[FGCS'24] GenArchBench: A genomics benchmark suite for arm HPC processors

L. López-Villellas, R. Langarita-Benı́tez, A. Badouh, V. Soria Pardos, Q. Aguado-Puig, G. López-Paradı́s, M. Doblas, J. Setoain, C. Kim, M. Ono, A. Armejach, S. Marco-Sola, J. Alastruey-Benedé, P. Ibáñez, M. Moretó. Future Generation Computer Systems, 2024. [paper]

2023

[MICRO'23] A Tensor Marshaling Unit for Sparse Tensor Algebra on General-Purpose Processors

M. Siracusa, V. Soria-Pardos, F. Sgherzi, J. Randall, D. J. Joseph, M. Moreto, A. Armejach. Proceedings of the 56th Annual International Symposium on Microarchitecture (MICRO 2023). [paper]

[ISCA'23] DynAMO: Improving Parallelism Through Dynamic Placement of Atomic Memory Operations

V. Soria-Pardos, A. Armejach, D. Suárez-Gracia, T. Mück, J. A. Joao, A. Rico, M. Moretó. Proceedings of the 50th Annual International Symposium on Computer Architecture (ISCA 2023). [paper]

[DCIS'23] Sargantana: An Academic SoC RISC-V Processor in 22nm FDSOI Technology

M. Doblas, et al. Conference on Design of Circuits and Integrated Systems (DCIS 2023). [paper]

2022

[DCIS'22] DVINO: A RISC-V Vector Processor Implemented in 65nm Technology

Guillem Cabo, et al. Conference on Design of Circuits and Integrated Systems (DCIS 2022), Pamplona. [paper]

[DSD'22] Sargantana: A 1 GHz+ In-Order RISC-V Processor with SIMD Vector Extensions in 22nm FD-SOI

Víctor Soria Pardos, Max Doblas, Guillem López-Paradís, Gerard Candón, Narcís Rodas, Xavier Carril, Pau Fontova-Musté, Neiel Leyva, Santiago Marco-Sola, Miquel Moretó. Euromicro Conference on Digital System Design (DSD 2022), Maspalomas. [paper]

2021

[JoS'21] On the use of many-core Marvell ThunderX2 processor for HPC workloads

Víctor Soria-Pardos, Adrià Armejach, Darío Suárez, Miquel Moretó. Journal of Supercomputing 77, 3315–3338 (2021). [paper]

[DCIS'20] An academic risc-v silicon implementation based on open-source components

Jaume Abella et al. Second Young Architect Workshop (YArch 2020). Conference on Design of Circuits and Integrated Systems (DCIS 2020), Segovia. [paper]

Honors and Awards

HiPEAC Paper Award

Awarded in three times

FPU Doctoral Fellowship

Funded by Spanish Government (MINECO)

Barcelona, Spain

Duration: 2021-2024

Contact

E-mail: victorsoriapardos@gmail.com or victor.soria@bsc.es