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Víctor Soria Pardos

SoC Interconnect Architecture Engineer @ Openchip & Teaching Assistant @ Universitat Politècnica de Catalunya (UPC)

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About Me

My name is Víctor Soria Pardos and I am a SoC Interconnect Architecture Engineer at Openchip and a Teaching Assistant at Universitat Politècnica de Catalunya (UPC). I received my Ph.D. in Computer Architecture from the UPC and the Barcelona Supercomputing Center (BSC-CNS). I also hold a Master in Innovation and Research in Informatics and a BSc from the UPC and Universidad de Zaragoza, respectively.

My expertise includes several topics of computer architecture. Specifically, focuses in CPU microarchitecture, parallel computing, cache coherence, synchronization, and domain specific accelerators. I've published in top-tier computer architecture conferences, including ISCA and MICRO. I've colaborated in different RISC-V open-source CPUs (Lagarto, DVINO and Sargantana).

Recent News

[2026] My PhD dissertation "Advanced atomics: leveraging memory hierarchies to improve atomic memory operations for next generation coherent manycores" received the Excelent, Cum Laude.
[2026] I've released the source code of DynAMO in my GitHub.
[2025] Delegato: Locality-Aware Atomic Memory Operations on Chiplets was nominated to the Best Paper Award at MICRO 25.
[2025] Our paper Delegato: Locality-Aware Atomic Memory Operations on Chiplets was accepted at MICRO 25.
[2025] Our paper FLAMA: Architecting Floating-Point Atomic Memory Operations for Heterogeneous HPC Systems was accepted at DSD 25.
[2023] I intershiped in Arm Sophia Antipolis for three months.
[2023] Our paper A Tensor Marshaling Unit for Sparse Tensor Algebra on General-Purpose Processors was accepted at MICRO 23.
[2023] Our paper DynAMO: Improving Parallelism Through Dynamic Placement of Atomic Memory Operations was accepted at ISCA 23.
[2022] Our paper Sargantana: A 1 GHz+ In-Order RISC-V Processor with SIMD Vector Extensions in 22nm FD-SOI got accepted at DSD 2022 and received the Outstanding Paper Award.
[2021] Arm has published a short blog entry about my research
[2021] Received the FPU Competitive Doctoral Fellowship by the Spanish Government after.

Education

Universitat Politècnica de Catalunya (UPC)

Ph.D. in Computer Architecture. Excellent, Cum Laude

2021 - 2026

Supervisors: Miquel Moretó and Darío Suárez

Thesis: Advanced atomics: leveraging memory hierarchies to improve atomic memory operations for next generation coherent manycores

Universitat Politècnica de Catalunya (UPC)

Master in Innovation and Research in Informatics. Specialization in High Performance Computing

2019 - 2022

Thesis: Characterization and modeling of atomic memory operations in arm based architectures

Universidad de Zaragoza (Unizar)

Bachelor's Degree in Informatics Engineering

2015 - 2019

One year abroad at Universitat Politècnica de Catalunya

Thesis: Characterization of HPC applications for ARM SIMD instructions

Caracterización de aplicaciones HPC para extensiones vectoriales de ARM

Professional Experience

Teaching Assistant @ Universitat Politècnica de Catalunya (UPC)

September 2023 - Now
  1. Computer Architecture (2023,2024,2025)
  2. Computer Architecture II (2024,2025)

SoC Interconnect Engineer @ OpenChip

January 2026 - Now
  1. Defining Cache Hierarchy, Coherence, NoC Architectures

First Stage Researcher (PhD Student) @ Barcelona Supercomputing Center (BSC-CNS)

September 2021 - January 2026
  1. Participation in Projects:
    • EPI SGA2
    • Arm Center of Excellence
    • ACAP: Arquitectura de Computadores de Altas Prestaciones
    • BZL: Barcelona Zettascale Lab
  2. Thesis: Advanced Atomics: Leveraging Memory Hierarchies to Improve Atomic Memory Operations for Next Generation Coherent Manycores

Junior Research Engineer @ Barcelona Supercomputing Center (BSC-CNS)

September 2019 - September 2021
  1. Participation in Projects:
    • Drac
    • Arm Center of Excellence
  2. Characterizing AMO in Arm machines

Undergraduate Research Student @ Barcelona Supercomputing Center (BSC-CNS)

September 2018 - September 2019
  1. Participation in Projects:
    • Montblanc 2020
  2. Characterizing SIMD extensions using OpenMP autovectorization

Publications

2025
[MICRO'25] Delegato: Locality-Aware Atomic Memory Operations on Chiplets
V. Soria-Pardos, A. Armejach, D. Suárez-Gracia, T. Mück, J. A. Joao, M. Moretó.. Proceedings of the 58th Annual International Symposium on Microarchitecture (MICRO 2025). [paper]
[DSD'25] FLAMA: Architecting Floating-Point Atomic Memory Operations for Heterogeneous HPC Systems
V. Soria-Pardos, A. Armejach, D. Suárez-Gracia, D. Martinot, A. Grasset, M. Moretó. Euromicro Conference on Digital System Design (DSD 2025), Salerno. [paper]
[RISC-V Summit Europe'25] REPTILES: Repeated Tiles of Sargantana,a RISC-V multicore based on OpenPiton
Noelia Oliete-Escuin, Arnau Bigas-Soldevila, Narcís Rodas, et al. RISC-V Summit Europe, Paris. [paper]
2024
[FGCS'24] GenArchBench: A genomics benchmark suite for arm HPC processors
L. López-Villellas, R. Langarita-Benı́tez, A. Badouh, V. Soria Pardos, Q. Aguado-Puig, G. López-Paradı́s, M. Doblas, J. Setoain, C. Kim, M. Ono, A. Armejach, S. Marco-Sola, J. Alastruey-Benedé, P. Ibáñez, M. Moretó. Future Generation Computer Systems, 2024. [paper]
2023
[MICRO'23] A Tensor Marshaling Unit for Sparse Tensor Algebra on General-Purpose Processors
M. Siracusa, V. Soria-Pardos, F. Sgherzi, J. Randall, D. J. Joseph, M. Moreto, A. Armejach. Proceedings of the 56th Annual International Symposium on Microarchitecture (MICRO 2023). [paper]
[ISCA'23] DynAMO: Improving Parallelism Through Dynamic Placement of Atomic Memory Operations
V. Soria-Pardos, A. Armejach, D. Suárez-Gracia, T. Mück, J. A. Joao, A. Rico, M. Moretó. Proceedings of the 50th Annual International Symposium on Computer Architecture (ISCA 2023). [paper]
[DCIS'23] Sargantana: An Academic SoC RISC-V Processor in 22nm FDSOI Technology
M. Doblas, et al. Conference on Design of Circuits and Integrated Systems (DCIS 2023). [paper]
2022
[DCIS'22] DVINO: A RISC-V Vector Processor Implemented in 65nm Technology
Guillem Cabo, et al. Conference on Design of Circuits and Integrated Systems (DCIS 2022), Pamplona. [paper]
[DSD'22] Sargantana: A 1 GHz+ In-Order RISC-V Processor with SIMD Vector Extensions in 22nm FD-SOI
Víctor Soria Pardos, Max Doblas, Guillem López-Paradís, Gerard Candón, Narcís Rodas, Xavier Carril, Pau Fontova-Musté, Neiel Leyva, Santiago Marco-Sola, Miquel Moretó. Euromicro Conference on Digital System Design (DSD 2022), Maspalomas. [paper]
2021
[JoS'21] On the use of many-core Marvell ThunderX2 processor for HPC workloads
Víctor Soria-Pardos, Adrià Armejach, Darío Suárez, Miquel Moretó. Journal of Supercomputing 77, 3315–3338 (2021). [paper]
[DCIS'20] An academic risc-v silicon implementation based on open-source components
Jaume Abella et al. Second Young Architect Workshop (YArch 2020). Conference on Design of Circuits and Integrated Systems (DCIS 2020), Segovia. [paper]

Honors and Awards

HiPEAC Paper Award

Awarded in three times

FPU Doctoral Fellowship

Funded by Spanish Government (MINECO)

Barcelona, Spain

Duration: 2021-2024

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© 2025 Víctor Soria Pardos